"Briefly stated, the Gell-Mann Amnesia effect is as follows. You open the newspaper to an article on some subject you know well. In Murray’s case, physics. In mine, show business. You read the article and see the journalist has absolutely no understanding of either the facts or the issues. Often, the article is so wrong it actually presents the story backward—reversing cause and effect. I call these the 'wet streets cause rain' stories. Paper’s full of them. In any case, you read with exasperation or amusement the multiple errors in a story, and then turn the page to national or international affairs, and read as if the rest of the newspaper was somehow more accurate about Palestine than the baloney you just read. You turn the page, and forget what you know." - Michael Crichton
Single resistor VGA output from an FPGA. VGA pins 13 and 14, vertical and horizontal sync are connected directly to the FPGA (Altera Cyclone II), pins 1-3 are RGB and connected all parallel and through a 100 ohm resistor to the FPGA. Pins 6-8 are ground.
|PLL is running at 25 MHz giving monochrome VGA output. Adding color would be relatively trivial.|
|magick convert -fuzz 40% -colors 8 -layers Optimize -delay 5 output.gif out.gif|
module vga(input clock, output VGA_HS, output VGA_VS, output B);
reg vga_HS, vga_VS;
reg [9:0] CounterX;
reg [8:0] CounterY;
reg [9:0] temporary;
reg [9:0] cntx;
reg [9:0] cnty;
reg [7:0] fnt[6399:0];
initial $readmemh("fnt.hex", fnt);
always @(posedge pll_clock)
CounterX <= CounterX + 1;
CounterX <= 0;
CounterY <= CounterY + 1;
CounterY <= 0;
temporary <= temporary + 1;
vga_HS <= (CounterX>640+16 & CounterX<800-48);
vga_VS <= (CounterY>400+12 & CounterY<449-35);
cntx <= CounterX + temporary;
cnty <= CounterY + (temporary >> 2);
pixvalue <= ((CounterX<640 & CounterY<400) & (CounterX & CounterY)) | ((CounterX>128 & CounterX<512 & CounterY>64 & CounterY<300) & (cntx & cnty));
pixvalue <= (fnt[CounterX+CounterY*760]>1);
assign VGA_HS = ~vga_HS;
assign VGA_VS = ~vga_VS;
assign B = pixvalue;
altpll0 altpll0(.inclk0(clock), .c0(pll_clock));
Output from a 1k resistor ladder DAC (3 resistors) with Cyclone II.
Driven by LVDS serializers at 500 MHz.
|Simulation of quadrature signals from parametrically amplified quantum noise in a superconducting tunnel junction.|
Stability through slavery.